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CY62136V MoBLTM CY62136V18 MoBL2TM
128K x 16 Static RAM
Features
* Low voltage range: -- CY62136V18: 1.65V-1.95V * * * * * -- CY62136V: 2.7V-3.6V Ultra-low active, standby power Easy memory expansion with CE and OE features TTL-compatible inputs and outputs Automatic power-down when deselected CMOS for optimum speed/power put/output pins (I/O0 through I/O 15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O 0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O 8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O 7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O 8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. The CY62136V and CY62136V18 are available in 48-ball FBGA and standard 44-pin TSOP Type II (forward pinout) packaging.
Functional Description
The CY62136V and CY62136V18 are high-performance CMOS static RAMs organized as 131,072 words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBLTM) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH). The in-
Logic Block Diagram
Pin Configurations
TSOP II (Forward) Top View A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
DATA IN DRIVERS
A9 A7 A6 A3 A2 A1 A0
128K x 16 RAM Array 1024 X 2048
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE CE OE BLE
62136V-1
A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
62136V-2
ROW DECODER
More Battery Life and MoBL are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
A10 A11 A12 A13 A14 A15 A16
*
SENSE AMPS
3901 North First Street
*
San Jose
*
CA 95134
*
408-943-2600 January 20, 2000
CY62136V MoBLTM CY62136V18 MoBL2TM
Pin Configuration (continued)
FBGA Top View 1 BLE I/O 8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O 11 I/O12 I/O 13 NC A8 3 A0 A3 A5 NC NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O 5 WE A11 6 NC I/O0 I/O2 VCC VSS I/O 6 I/O7 NC A B C D E F G H
62136V-3
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C Supply Voltage to Ground Potential..................-0.5V to +4.6V
DC Voltage Applied to Outputs in High Z State[1] ....................................... -0.5V to VCC + 0.5V DC Input Voltage[1].................................... -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Device CY62136V18 CY62136V Industrial Industrial Range Ambient Temperature -40C to +85C -40C to +85C VCC 1.65V to 1.95V 2.7V to 3.6V
Product Portfolio
Power Dissipation (Industrial) VCC Range Product CY62136V CY62136V18 VCC(min) 2.7V 1.65 VCC(typ) 3.0V 1.80
[2]
Operating (ICC) VCC(max) 3.6V 1.95 Speed 70 ns 70 ns Typ.[2] 7 mA 3 mA Maximum 15 mA 7 mA Typ.[2] 1 A 1 A
Standby (ISB2) Maximum 15 A 15
Shaded areas contain preliminary information. Notes: 1. VIL (min) = -2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25C.
2
CY62136V MoBLTM CY62136V18 MoBL2TM
Electrical Characteristics Over the Operating Range
CY62136V Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs CE > V CC-0.3V, VIN > VCC-0.3V or VIN < 0.3V, f = fMAX CE > V CC-0.3V VIN > VCC-0.3V or VIN < 0.3V, f = 0 VCC = 3.6V LL 1 VCC = 3.6V Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V 2.2 -0.5 -1 -1 +1 +1 7 Min. 2.4 0.4 VCC + 0.5V 0.8 +1 +1 15 Typ.[2] Max. Unit V V V V A A mA
1
2
mA
100
A
ISB2
15
A
CY62136V18 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled IOUT = 0 mA, f = fMAX = 1/tRC, CMOS levels IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB1 Automatic CE Power-Down Current-- CMOS Inputs Automatic CE Power-Down Current-- CMOS Inputs CE > V CC-0.3V, VIN > VCC-0.3V or VIN < 0.3V, f = fMAX CE > V CC-0.3V VIN > VCC-0.3V or VIN < 0.3V, f = 0 VCC = 1.95V LL 1 VCC = 1.95V Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 1.65V VCC = 1.65V VCC = 1.95V VCC = 1.65V 1.4 -0.5 -1 -1 +1 +1 3 Min. 1.5 0.2 VCC + 0.3V 0.4 +1 +1 7 Typ.[2] Max. Unit V V V V A A mA
1
2
mA
100
A
ISB2
15
A
Capacitance[3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC= VCC(typ) Max. 6 8 Unit pF pF
Note: 3. Tested initially and after any design or process changes that may affect these parameters.
3
CY62136V MoBLTM CY62136V18 MoBL2TM
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC Typ 10% GND < 5 ns
62136V-4
ALL INPUT PULSES 90% 90% 10% < 5 ns
62136V-5
Equivalent to:
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters R1 R2 RTH VTH
Shaded areas contain preliminary information.
3.0V 1105 1550 645 1.75V
1.8V 15294 11300 6500 0.85V
UNIT Ohms Ohms Ohms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR VDR ICCDR Description VCC for Data Retention (CY62136V18) VCC for Data Retention (CY62136V) Data Retention Current VCC = 1.0V CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V No input may exceed VCC+0.3V LL Conditions[5] Min. 1.0 1.0 0.1 Typ.[2] Max. 1.95 3.6 5 Unit V V A
tCDR[3] tR[4]
Chip Deselect to Data Retention Time Operation Recovery Time
0 100
ns s
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min.)
tCDR
VDR > 1.0 V
VCC(min.)
tR
CE
62136V-6
Notes: 4. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ., and output loading of the specified IOL/IOH and 30 pF load capacitance.
4
CY62136V MoBLTM CY62136V18 MoBL2TM
Switching Characteristics Over the Operating Range[5]
70 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE CYCLE[8, 9] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High Z WE HIGH to Low Z
[6, 7] [6]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z
[6] [6, 7]
Min. 70
Max.
Unit ns
70 10 70 35 5 25 10 25 0 70 35 5 25 70 60 60 0 0 50 60 30 0 25 10
[6, 7] [8]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z CE HIGH to High Z
CE LOW to Low Z[6]
[6, 7]
CE LOW to Power-Up CE HIGH to Power-Down BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z BLE / BHE HIGH to High Z
Switching Waveforms
Read Cycle No. 1
[10, 11]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
62136V-7
Notes: 6. At any given temperature and voltage condition, t HZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle.
5
CY62136V MoBLTM CY62136V18 MoBL2TM
Switching Waveforms (continued)
Read Cycle No. 2 [11, 12]
CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB
62136V-8
tRC tPD tHZCE
tHZOE
HIGH IMPEDANCE DATA VALID
ICC
[8, 13, 14]
Write Cycle No. 1 (WE Controlled)
tWC ADDRESS
CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 15 tHZOE
Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied.
tHD
DATAIN VALID
62146V-9
6
CY62136V MoBLTM CY62136V18 MoBL2TM
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)
[8, 13, 14]
tWC ADDRESS CE tSA tAW tHA tSCE
BHE/BLE
tBW
WE
tPWE tSD tHD
DATA I/O
DATA VALID IN
62136V-10
Write Cycle No. 3 (WE Controlled, OE LOW)
[9, 14]
tWC ADDRESS
CE tAW tBW tSA tHA
BHE/BLE WE
tSD DATA I/O NOTE 15 tHZWE DATA VALID IN
tHD
tLZWE
62136V-11
7
CY62136V MoBLTM CY62136V18 MoBL2TM
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 NORMALIZED ICC 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 3.7 VIN =VCC typ. TA =25C I CC ISB2 A 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 SUPPLY VOLTAGE (V) VCC =VCC typ. VIN =VCC typ. STANDBY CURRENT vs. AMBIENT TEMPERATURE
ISB
-55
25
105
AMBIENT TEMPERATURE (C)
NORMALIZED STANDBY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC 1.2 NORMALIZED ISB 1.0 0.8 0.6 0.4 0.2 0.0 1.0 VIN =VCC typ. TA =25C I SB2
NORMALIZED I CC vs. CYCLE TIME 1.50 VCC =3.6V TA =25C
1.00
0.50
0.10 1.9 2.8 3.7
1
5
10
15
CYCLE FREQUENCY (MHz) SUPPLY VOLTAGE (V)
Truth Table
CE H L L L L L L L L L WE X H H H H H H L L L OE X L L L H H H X X X BHE X L H L L H L L H L BLE X L L H L L H L L H Inputs/Outputs High Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O 15); I/O0-I/O7 in High Z High Z High Z High Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O 15); I/O0 -I/O7 in High Z Read Read Read Deselect/Output Disabled Deselect/Output Disabled Deselect/Output Disabled Write Write Write Mode Deselect/Power-Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
8
CY62136V MoBLTM CY62136V18 MoBL2TM
Ordering Information
Speed (ns) 70 Ordering Code CY62136VLL-70ZI CY62136VLL-70BAI CY62136V18LL-70BAI
Shaded areas contain preliminary information.
Package Name Z44 BA48 BA48 44-Pin TSOP II
Package Type 48-Ball Fine Pitch BGA 48-Ball Fine Pitch BGA
Operating Range Industrial
Document #: 38-00728-*B
Package Diagrams
48-Ball (7.00 mm x 7.00 mm) FBGA BA48
51-85096-A
9
CY62136V MoBLTM CY62136V18 MoBL2TM
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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